Line end voids defectivity improvement on 64 pitch Cu wire interconnects of 14 nm technology

Semiconductor manufacturing of 14 nm devices has presented numerous engineering and manufacturing challenges from newly introduced FinFETs in the FEOL to double patterned trenches and self-aligned vias in the BEOL. Voids are a common defect found in the metal interconnects of the BEOL of any technology, more generally occurring in the thinner pitch size copper metal wires. Voids manifest themselves in many forms like line voids, island voids, seam voids, line end voids, point voids, etc., depending on the location, orientation and mechanism of occurrence. Small process marginality between the CuMn seed deposition and Cu plating processes is the primary source of voids in Cu interconnects. In this paper, we will discuss in-line LEV inspection solutions as well as the causes and methods to improve line end voids (LEV) in 64 nm pitch Cu-wire interconnects for the 14nm technology node.