High-Speed Serializer for a 64 GS s −1 Digital-to-Analog Converter in a 28 nm Fully-Depleted Silicon-on-Insulator CMOS Technology

Abstract. An attractive solution to provide several channels with very high data rates of tens of Gbit s −1 for digital-to-analog converters (DACs) in arbitrary waveform generators (AWGs) is to use a high speed serializer in front of the DAC. As data sources, on-chip memories, digital signal processors or field-programmable gate arrays can be used. Here, we present a serializer consisting of a 19 channel 16:1 multiplexer (MUX) for output data rates up to 64 Gbit s −1 per channel and a low skew ( ∼  8.8  ps ) two-phase frequency divider and clock distribution network that is completely realized in static CMOS logic. The circuit is designed in a 28  nm Fully-Depleted Silicon-on-Insulator (FD-SOI) technology and will be used in an 8  bit 64 GS s −1 DAC between the on-chip memory and the DAC output stage. Due to a four bits unary and four bits binary segmentation, a 19 channel MUX is required. Simulations on layout level reveal a data-dependent peak-to-peak jitter of less than 1.8  ps at the output of one MUX channel with a total average power consumption of approximately 1.15  W of the whole MUX and clock network.