Implementation of the reconfiguration port scheduling on the erlangen slot machine

Despite the possibility to execute several hardware tasks in parallel on an FPGA, partial reconfiguration is sequential. There exist only one reconfiguration port which is used exclusively during the reconfiguration of a task. Single processor scheduling algorithms for task reconfiguration with preemption are evaluated in a real time application implemented on the Erlangen Slot Machine. The Erlangen Slot Machine besides having reconfigurable connection of peripherals to pins of the FPGA, offers a large Virtex II FPGA, in which a reasonable number of slots can be implemented. In the example, the scheduling algorithm is implemented on the PowerPC processor available on the board. Among other results, preemption in the reconfiguration phase is shown.