Global and Local Process Variation Simulations in Design for Reliability approach

Design for reliability (DfR) is of prime interest for integrated circuits designer to qualify IPs reliability and enable risk assessment. Currently developed models are composed of all wear-out mechanisms (HCI, BTI, and TDDB) but they are based on typical degradation shifts. In order to improve the modeling accuracy and enable designers to simulate a worst case, the reliability design flow should take into account process variations. This paper presents a new framework for process variations simulation combined with aging modeling. Firstly, margins are introduced in DfR equations to describe the additional degradations due to the lot-to-lot fabrication dispersion. The margins optimization is performed based on experimental measurements. Secondly, the impact of wafer-level variation is investigated through aging simulations nested in Monte Carlo (MC) flow. A new feature of MC analysis has been developed to describe separately the statistical variations at initial time and the ones induced by aging mechanisms. Both implementations are demonstrated using CMOS 65nm technology as test case. Finally, simulation results for a basic digital circuit are discussed to illustrate the complete DfR approach.