Parallel information and computation with restitution for noise-tolerant nanoscale logic networks

Nanoelectronic devices are anticipated to become exceedingly noisy as they are scaled towards thermodynamic limits. Hence the development of nanoscale classical information systems will require optimal schemes for reliable information processing in the presence of noise. We present a novel, highly noise-tolerant computer architecture based on the work of von Neumann that may enable the construction of reliable nanocomputers comprised of noisy gates. The fundamental principles of this technique of parallel restitution are parallel processing by redundant logic gates, parallelism in the interconnects between gate resources and intermittent signal restitution performed in parallel. The results of our mathematical model, verified by Monte Carlo simulations, show that nanoprocessors consisting of gates incorporating this technique can be made 90% reliable over 10 years of continuous operation with a gate error probability per actuation of and a redundancy of . This compares very favourably with corresponding results utilizing modular redundant architectures of with , and with no noise tolerance. Arbitrary reliability is possible within a noise limit of , with massive redundancy. We show parallel restitution to be a general paradigm applicable to different kinds of information processing, including neural communication. Significantly, we show how our treatment of para-restituted computation as a statistical ensemble coupled to a heat bath allows consideration of the computation entropy of logic gates, and tentatively sketch a thermodynamic theory of noisy computation that might set fundamental physical limits on scaling classical computation to the nanoscale. Our preliminary work indicates that classical computation may be confined to the macroscale by noise, quantum computation possibly being the only information processing possible at the extreme nanoscale.