MO‐E‐L100J‐02: Limits On Achievable Performance Levels for Active Matrix Flat Panel Imagers Incorporating Active Pixel Sensor Architectures

Purpose: The relatively high level of additive noise in active matrix flat‐panel imagers (AMFPIs) leads to significant loss of DQE under conditions of low exposures per frame and/or high spatial frequencies. One promising method for dealing with such performance loss involves in‐pixel signal amplification through incorporation of additional circuitry to each pixel — a concept generally referred to as an active pixel sensor. In this presentation, an examination of performance levels that can be achieved with active pixel sensors based on thin‐film electronics will be presented. Method and Materials: Calculations of the DQE of various active pixel sensor designs were performed using the cascaded systems formalism. Inputs to the calculations come from empirical measurements, published data, analytic calculations, and results derived from detailed circuit simulations. The calculations were performed for a series of designs, under fluoroscopic irradiation conditions, and using various readout protocols. Results: Our model calculations indicate that, under conditions of low exposure and/or high spatial frequency, substantial DQE restoration can be achieved via a combination of in‐pixel amplification circuitry and correlated double sampling protocols — each specifically selected to eliminate specific noise contributions. In particular, it appears feasible to reduce thermal noise associated with the pixel reset TFT and preamplifier noise to negligible levels and thereby increase DQE. However, the degree of performance improvement that can be practically realized will also depend upon the quality and properties of the thin film transistors used in the pixel circuit as well as selection of circuits that will yield well in manufacture. Conclusion: The degree of performance improvement made possible through array architectures comprising active pixel sensors is critically dependent on many factors including the properties of the transistors, the engineering rules governing pixel and array design, the choice of pixel circuit, and the method of array readout.