Physical simulation for verification and OPC on full chip level

In this paper, we introduce a rigorous OPC technology that links the physical lithography simulation with the OPC. Firstly, the various aspects of the rigorous OPC, related to process flow, are discussed and the practical feasibility of the embedded rigorous verification is taken into account, which can make the rigorous treatment of the full-chip level possible without any additional manual efforts. We explain an embedded rigorous verification flow and the basic structure of its functionality. Finally, its practical application to real cases is discussed.