A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC with Double Clock-Rate Coarse Decision

A SAR-assisted SAR ADC that uses a double clock-rate coarse decision technique is presented. The coarse ADC operates with a higher rate clock to reduce the MSBs decision time. The mismatch problem between coarse and fine ADCs is solved by using redundancy and background offset calibration. A simple metastability reduction technique for non-binary SAR ADC that does not require a lookup table is also proposed. The ADC core occupies a 0.0128-mm2 area and consumes 1.9 mW under a 1-V supply. With an 80-MHz input, the ADC achieves an SNDR of 58.1 dB and an SFDR of 72.1 dB. The peak DNL and INL are 0.96 LSB and 1.6 LSB, respectively, and the figure of merit is 24.26 fJ/conversion-step.