Multi-channel high-speed digital-to-analogue converter (DAC) synchronization method

The present invention provides a multi-channel high speed DAC synchronization implemented method comprising the following steps: First, FPGA-MASTER reference signal source generates a digital signal, a synchronous clock signal and the reset signal, and simultaneously transmits these signals to the FPGA-SLAVEP and DACM and coarse multipath delay, the P, M are positive integers; then, the FPGA-MASTER synchronous clock in FPGA-SLAVEP phase, and the phase delay module through a fine adjustment is 0; Finally, FPGA- SLAVEP performed DACM reference clock phase, and the phase delay module through a fine adjustment to zero. The present invention enables synchronization of the phase of the output signal, at the same time can be cascaded multi-chip multi-chip high-speed FPGA and DAC, DAC limit the clock speed is not performed and the phase of the phase modulation by the FPGA-MASTER and DAC FPGA-SLAVE, achieved FPGA-mASTE, and in phase with FPGA-SLAVE DAC data, so that the brightest full synchronization timing DAC controllable, improve efficiency and expand the output signal bandwidth.