Effects of Anneal and Silicon Interface Passivation Layer Thickness on Device Characteristics of In0.53Ga0.47As Metal-Oxide-Semiconductor Field-Effect Transistors

In this letter, we demonstrate an In 0.53 Ga 0.47 As channel n-type metal-oxide-semiconductor field-effect transistor (MOSFET) with silicon interface passivation layer (IPL) and HfO 2 gate oxide. The effects of the source/drain activation temperature, postdeposition annealing temperature, and thickness of silicon IPL on the transistor characteristics have been investigated. The results suggest that the annealing temperatures are critical for determining the transistor performances. Even though In 0.53 Ga 0.47 As is easier to obtain the unpinned surface Fermi level compared to GaAs, applying silicon IPL still improves the In 0.53 Ga 0.47 As nMOSFET characteristics significantly through engineering the HfO 2 /In 0.53 Ga 0.47 As interface quality.