Theoretical Considerations on the Optimal Performance of Sub-100 Nanometer Top-Gated Graphene Field-Effect Transistors

The operation and performance of top-gated sub-100 nanometer graphene channel field-effect transistors were investigated. The device model is designed for graphene with a narrow energy band gap epitaxially grown on the SiC substrate. The issue of graphene-metallic lead coupling is appropriately taken into account. By assuming the graphene-metal physisorption contact, a self-consistent calculation reproduces two regions of high carrier density at the ends of the graphene channels underneath the metallic leads according to the charge transferred effect between the metallic lead surface and graphene. The charge carrier densities in these source and drain regions, however, are not pinned, but vary with respect to the drain and gate voltages. It is shown that, in general, the graphene channel supports the ambipolar characteristics for all device samples, but for the samples with the channels shorter than 40 nm, the current-voltage characteristic takes the exponential law. Particularly, the current saturation with a rather small output conductance of 126 S/m was observed in a sufficiently large range of drain voltage due to the dominance of the thermionic emission and conventional tunneling mechanisms to the band-to-band tunneling. A rough assessment of the device performance was also carried out. It reveals an extremely high cutoff frequency in the order of \(10^3\hbox { GHz}\) and a linear scaling rule for transistors with the channel length longer than 40 nm. The behaviour and magnitude of these quantities are consistent with an experimental study of sub-100 nm devices fabricated using the self-alignment technique.