A 30Gb/s 2x Half-Baud-Rate CDR

This paper presents a 2x half-baud-rate clock and data recovery technique that locks to the edge by performing 2x oversampling at half-baud-rate (every other UI). A test-chip was fabricated in TSMC 28nm HPC CMOS technology demonstrating a 30 Gb/s 2x half-baud-rate CDR with a Tyco 5” channel with 13.06 dB loss at Nyquist. The total power consumption is measured to be 79.2 mW (FOM of 2.64 pJ/bit) for 30 Gb/s PRBS31 input data.