A Parallel Arithmetic Unit

Abstract : A parallel arithmetic unit for digital computers is fitted with two pairs of registers, each divided into a digit sum register and a digit transfer register. Each register has on its input AN and GATE which lies in a feedback circuit to input elements of the register in the other pair, AN and GATE to carry out the logic operations, and a three input adder. The clear signals are passed to each and GATE and adder through control wires. (Author)