Estimation of Switching Losses using Simplified Compact Models for SiC Power MOSFETs

For automated design procedures of power electronic systems, the switching loss energy, E SW , of power semiconductor devices as design parameters have to be estimated at very low computational cost by using simplified analytical models. The analytical models are calibrated using the I-V and C-V characteristics from device datasheets, which are typically provided only in a limited range of operating points. In this paper, the trade-offs between modeling complexity and accuracy when estimating E SW of power semiconductor devices is performed starting from a fully physics-based model. The two-voltage-dependent I-V and C-V device characteristics are extracted by means of numerical (TCAD) device simulations for a wide range of operating points. The accuracy of calculating the switching energy losses when employing simplified models for layout parasitics and the I-V and C-V device models derived from datasheets is investigated on an example of a planar-gate 1.2 kV 80mΩ SiC power MOSFET. It is shown that by carefully designing an equivalent model of layout parasitics, the actual switching losses can be modeled based on data-sheet information with less than 10% relative error.