Reversible MEDD gate as a MUX, Encoder, De-MUX and Decoder

Reversible Logic supports the process of running a system both forward and backward. This technique can be used to reduce the power dissipation in VLSI and can be applied to Low Power CMOS, DNA computing, nanotechnology and quantum computation. An experimental reversible gate MEDD is initiated in this paper that aims to function as a 2:1 Multiplexer, 4:2 Encoder, 1:2 De-multiplexer and a 2:4 Decoder simultaneously. This is a design which works as four combinational circuits concurrently. The design is implemented and tested on FPGA XC3S400-5PQ208. This proposal is designed for less power dissipation along with reduction in complexity and space. Power dissipation of the gate is found to be 0.479mW. Further analysis of the proposed gate is done by studying the simulation results obtained by varying the supply voltage to the gate and by changing input vectors to the gate keeping supply voltage constant.