A 77.2-dB SNDR SAR ADC With a Segmented Comparator Logic Based on Compensatory SA Latch for FIA

This paper presents a successive approximation register (SAR) analog-to-digital convertor (ADC) dedicated to Internet of Things (IoT) applications. A segmented comparator logic with separated amplification phase and latch phase is proposed which enables sufficient amplification to achieve high resolution. Cooperating with the logic, a compensatory strong-arm (SA) latch is proposed for the floating invertor pre-amplifier (FIA), which guarantees both high gain and output stability of FIA. Implemented in 110nm CMOS technology, at a 1.5-V supply and 1 MS/s, the ADC achieves an SNDR of 77.2 dB and consumes 348 µw, resulting in a figure of merit (FoM) of 168.8 dB.