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A CLB architecture for Online correction of SEU-based Errors in LUTs of SRAM-based FPGAs
A CLB architecture for Online correction of SEU-based Errors in LUTs of SRAM-based FPGAs
2005
E. Syam Sundar Reddy
Vikram Chandrasekhar
Milagros Sashikánth
Kamakoti V
Narayanan Vijaykrishnan
Keywords:
Parallel computing
Field-programmable gate array
Static random-access memory
Architecture
Computer science
Embedded system
Correction
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