1.45-fJ/bit Access Two-Port SRAM Interfacing a Synchronous/Asynchronous IoT Platform for Energy-Efficient Normally Off Applications

This letter presents a single-rail two-port static random-access memory (SRAM) designed in 28-nm FD-SOI technology specifically for a synchronous/asynchronous Internet of Things node. This SRAM supports an asynchronous interface communication and a fast transition sleep/active mode. It enables simultaneous synchronous and asynchronous accesses on its two independent ports, as well as a selective virtual ground (SVGND) to support ultralow voltage in read operations. Measurements on a 64-kb memory macro prove the functionality for a supply voltage ranging from 0.25 to 1.25 V. The sleep mode enables $158\times$ reduction of the SVGND static-power consumption. The SVGND read assist achieves a gain of 50 mV on the read port operations lowest voltage. The memory achieves, at 0.25 V and 27 °C, an average energy cost per access of 1.45 fJ/bit at 451 kHz and a leakage of 25 pW/bit in sleep mode.