The Design and Implementation of Bit Synchronized Circuit with Changeable Performance

This paper introduces the principle of traditional digital phase—locked loop.An improved method of bit synchronization with changeable performance based on FPGA is presented.Phase difference between the local synchronization signal and the received symbols is got by phase comparator.Using the phase difference controls the counter.The counter controls the number of adding or deleting pulses in the corresponding gate.The max phase error and synchronization build time can be changed through the setting of different K.