Module selection method with improved capacitor voltage balance for MMC using (2 N + 1) SHEPWM

Abstract For modular multilevel converters (MMCs) used in medium-voltage applications, (2 N + 1) selective harmonic elimination PWM ((2 N + 1) SHEPWM) is widely used. Since it has N more output voltage levels than traditional (N + 1) SHEPWM, and can provide control of more low-order harmonics. However, the N more levels are acquired through inserting (N + 1) or (N-1) submodules (SMs) in each leg. This will worsen capacitor voltage balancing performance. To maintain capacitor voltage balancing in SHEPWM, the most commonly-used voltage-balancing strategy is module selection method that selects the capacitor of the maximum or minimum voltage to insert or bypass according to the direction of arm current. Nevertheless, the module selection method only works when the number of inserting SMs changes. It cannot guarantee the balance among SMs between these moments. Our paper proposes a new module selection method with improved capacitor voltage balance. This new balance method only needs to add a few moments of maximum arm power to maintain capacitor voltage balancing throughout the whole fundamental period. The proposed method includes three steps. Firstly, ±45° time periods centered around the maximum power instants are selected according to various power angles. Then the maximum and minimum of average capacitor voltage of the same arm are calculated online and used as upper and lower limits to keep each capacitor voltage within range. Finally, 5%~10% of the range is utilized to limit the difference among all the capacitor voltages in the same arm. The performance of the proposed method is validated by simulations and experiments.