Mask specification guidelines in spacer patterning technology
2008
We have studied both the mask CD specification and the mask defect specification for spacer patterning
technology (SPT). SPT has the possibility of extending optical lithography to below 40nm half-pitch devices. Since
SPT necessitates somewhat more complicated wafer process flow, the CD error and mask defect printability on wafers
involve more process factors compared with conventional single-exposure process (SEP). This feature of SPT implies
that it is very important to determine mask-related specifications for SPT in order to select high-end mask fabrication
strategies; those are for mask writing tools, mask process development, materials, inspection tools, and so on. Our
experimental studies reveal that both mask CD specification and mask defect specification are somehow relaxed from
those in ITRS2007. This is most likely because SPT reduces mask CD error enhanced factor (MEF) and the reduction
of line-width roughness (LWR).
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