Low Frequency Noise Considerations for CMOS Analog Circuit Design

This paper gives an overview on 1/f‐noise issues relevant for today’s CMOS analog circuit design. The device‐to‐circuit relation of noise and the relevant operating conditions are reviewed. Modeling of the biasing dependence of 1/f‐noise amplitude including large signal and statistical effects are discussed. The noise corner frequency is shown to increase with CMOS technology scaling, and statistical effects are shown to even scale worse compared to the 1/f‐noise. Moreover circuit design measures against noise are investigated. Finally, reliability issues concerning 1/f‐noise in analog circuits are reviewed.