A Process for Strained Silicon n-Channel HMOSFETs

High electron mobility strained silicon n-channel heterostructure MOSFETs with sub-micron channel lengths have been investigated by numerical simulation and appropriate close-to-conventional device processing technologies have been developed. The requirement to avoid relaxation and interdiffusion of the strained silicon layer which is bounded by relaxed SiGe alloy sets a limit on the total thermal budget. Processing of n-channel MOSFETs on silicon substrates with a maximum temperature of 810°C has been successfully demonstrated.