InP DHBT technology and design for 40 Gbit/s full-rate-clock communication circuits
2002
In this paper, we present our InP DHBT technology with improved performances, yield and uniformity; and some new design tools, both of which have allowed us to achieve 40+ Gbit/s full-rate-clock circuits, such as the D-flip-flop. These circuits have been characterized and packaged.
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