Efficient Multiplier and FPGA Implementation for NTRU Prime

As quantum computing age is emerging on horizon, many of the current cryptography standards, e.g., RSA and Elliptic Curve Cryptography, are shown to be compromised under quantum attacks according to Shor's algorithm. A multiple-round competition has been launched by NIST to decide the next generation post-quantum cryptography (PQC) standards since 2017. Entering the final round, NTRU Prime system, proposed in 2016, remains one of a few that have a chance to be part of the future PQC standard. In this work, efficient multiplication architecture is proposed for Streamlined NTRU Prime system. To the best of our knowledge, this work is the first attempt at hardware architecture and implementation of NTRU prime system. Our FPGA implementation results have also shown the proposed multiplier compares favorably to the similar work on the original NTRU system.