Challenges in Assembly and Reliability of Thin NAND Memory Die

To stack more NAND memory dice in a package or to reduce package thickness, die thickness has to be thinner and thinner. This paper discusses the significant challenges associated with thin die in assembly process and device level reliability. A single die NAND memory ball grid array package was assembled with 4 different die thicknesses as a test vehicle to go through assembly process, temperature cycling, and electrical characterization. The main issues observed during assembly are discussed in light of the dependence of "floating" die and pad cracking on die thickness and dicing recipe. The effects of surface contact load during die attach and wire bond on the deformation of memory die were analyzed with the finite element method. The finite element model provides insight into the deformation behavior of memory die in terms of die thickness, die attach film mechanical properties, and die attach process defects. The end of life reliability was also investigated in this study. Thinner dice show more growing bad blocks during cycling, which could be due to latent damage to the dielectric layers from mechanical stress during prolonged wafer thinning process. However, different processes with the same thickness differ significantly and fine tuning of the wafer thinning process can help mitigate the damage during thinning. If the memory blocks do survive the cycling, they actually show similar cell characteristic such as failure bit counts and threshold voltage distributions. This indicates that the intrinsic property of the NAND cells doesn't significantly degrade for the thickness level studied in this paper.