Unlocking FPGAs Using High Level Synthesis Compiler Technologies

FPGA devices have long been the standard for massively parallel computing fabrics with a low power footprint. Unfortunately, the complexity associated with an FPGA design has limited the rate of adoption by software application programmers. Recent advances in compiler and FPGA fabric capabilities are reversing this trend and there is a growing adoption of FPGAs for algorithmic workloads such as data analytics, feature detection in images, adaptive beam forming, etc. One of the pillars of this shift is the Vivado HLS compiler, which enables the compilation of algorithms captured in C and C++into efficient FPGA implementations. This talk focuses on how the HLS compiler creates algorithm specific compute architectures and how these elements are then used in an OpenCL based system level design abstraction. The evolution of these hardware design abstractions into software centric specifications enable application developers to leverage the flexibility of the FPGA fabric without the constraints typically found in fixed parallel architectures such as multi-core CPUs/GPUs.