Demonstration of Ge Nanowire CMOS Devices and Circuits for Ultimate Scaling

In this paper, Ge nanowire (NW) CMOS devices and circuits are analyzed in detail. Various experiment splits are studied, including device geometry parameters such as the channel lengths ( $L_{\mathrm{ ch}}$ ) from 100 to 40 nm, a NW height ( $H_{\mathrm{ NW}}$ ) of 10 nm, the NW widths ( $W_{\mathrm{ NW}}$ ) from 40 to 10 nm, and the dielectric equivalent oxide thicknesses (EOTs) of 2 and 5 nm, and four types of device operation modes of accumulation mode (AM) and inversion mode (IM) n-type MOSFETs and p-type MOSFETs. Benefited from the NW structure with scaled EOT, subthreshold swing (SS) as low as 64 mV/dec and maximum transconductance ( $g_{\max }$ ) as high as $1057~\mu \text{S}/\mu \text{m}$ are obtained on the Ge NW nMOSFETs. The NW pMOSFETs are also realized on the same common substrate. Furthermore, hybrid Ge NW CMOS with AM nMOSFET and IM pMOSFET is demonstrated for the first time on a Si substrate. The highest maximum voltage gain reaches 54 V/V in the Ge NW CMOS inverters.