Compilation and Wear Leveling for Programmable Logic-in-Memory Architecture

This chapter presents an efficient and fully automated compilation procedure to translate arbitrary Boolean functions into programs for a standard logic-in-memory computer architectures based on MIGs. The chapter also addresses endurance constraints within resistive in-memory architectures. This highly matters due to the fact that RRAM devices suffer from quite low write endurance, despite being superior to conventional memories in many aspects. In this context, this chapter also presents techniques for balancing memory write traffic as a solution to extend the lifetime of resistive crossbar architectures.