Application Specific True Critical Paths Identification in Sequential Circuits

The extreme complexity of digital systems enabled by nanometer-scale implementation technologies comes along with strengthened design requirements that are difficult to achieve with the conventional techniques. Over-designing beyond the minimal required guarantees may have negative impacts on the overall system’s cost. In this paper we focus on the task of timing-critical logic paths identification in digital systems that has many applications in design and test field, like verifying the timing constraints of designs, estimating critical delays, Simulating path delay faults and reliability analysis such as ageing. The contribution is a new scalable simulation-based hierarchical search method for application-specific online-viable true critical paths identification in sequential circuits. The approach is motivated by the concept of mixed-critical systems, but it can be applied for any type of digital system. We propose to represent the circuits hierarchically at the level of higher level submodules using t e theory of Structurally Synthesized BDDs (SSBDD). The search space is limited by the application-specific context that enables accurate results even for complex sequential circuits. Experimental results demonstrate efficiency of the proposed approach, and considerable reduction of the length of critical paths if the application-specific constraints are taken into account.