A 14nm 100Kb 2T1R Transpose RRAM with >150X resistance ratio enhancement and 27.95% reduction on energy-latency product using low-power near threshold read operation and fast data-line current stabling scheme

This study proposes an 2T1R Transpose RRAM (T-RRAM) macro supports highly efficient transpose accessibility featuring (1) a 2T1R cell with low-power near-threshold-voltage (NTV) read operations for resistance ratio (R-ratio) enhancement (>150X) and read disturb suppression, and (2) a customized macro structure with fast data-line current stabling scheme (FDCS) to reduce the energy-latency product (27.95%). A 100Kb 2T1R T-RRAM macro is silicon verified using 14nm CMOS process with TaOx-based RRAM. This paper firstly demonstrates a 14nm T-RRAM with large R-ratio, small area overhead and improved energy-latency product.