Hardware-Software-Co-Synthese zur Verbesserung der Fehlertoleranz

Embedded systems consist of hardware and software and are ubiquitous in safety critical fields, e.g., aerospace. The increasing integration density of modern, digital circuits causes an increasing vulnerability of embedded systems to transient faults. Techniques to protect embedded systems against transient faults, i.e., to increase the fault tolerance of the systems, are often either implemented only in hardware or only in software. In this paper, we focus on the synthesis of techniques to improve the fault tolerance of embedded systems considering hardware and software. We use a new approach based on model checking to assess the fault tolerance of software programs utilizing their machine code. In this approach, we embed an existing method for assessing fault tolerance for hardware. Moreover, we present an iterative algorithm for assessing the fault tolerance of an embedded system leveraging our approach and for synthesizing technique to improve the fault tolerant in hardware and software. We evaluate the algorithm in a case study using an embedded system which instructs aircraft to avoid collisions.