$1\times$ - to $2\times$ -nm perpendicular MTJ Switching at Sub-3-ns Pulses Below $100~\mu$ A for High-Performance Embedded STT-MRAM for Sub-20-nm CMOS

Magnetization switching is confirmed for sub-3-ns pulses below $100~\mu \text{A}$ in perpendicular magnetic tunnel junctions (MTJs) down to 16 nm in diameter. The magnetoresistance ratio exceeded 150%, satisfying requirements for fast read conditions. Using sub-30-nm MTJs, write-error rates of up to an order of −6 (10 −6 ) are demonstrated. Read and write current margins, which are important device designs, are sufficiently large to avoid read disturbances. Moreover, $1\times $ -to- $2\times $ -nm MTJs have sufficient data retention for level-2 or level-3 cache requirements. Furthermore, the MTJ resistance remains stable after 10 12 write events. To the best of our knowledge, this is the first demonstration of $1\times $ - to $2\times $ -nm MTJs supporting cache memory along with read–write current margins, fast read operations, low power consumption, sufficient retention, and high endurance.