Low noise clock synthesizer design using optimal bandwidth

This paper presents a salient method to design a low noise clock synthesizer for high-speed data processing applications. The proposed design method optimizes the loop bandwidth by using a discrete-time analysis of a PLL and minimizes the clock synthesizer output jitter. Computer simulation is performed and simulation results strongly support the theoretical analysis. A 900 MHz clock synthesizer is experimentally designed and shows the minimum jitter at the optimum bandwidth obtained from the analysis.