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Investigation of the area reduction by pass transistor logic in reconfigurable device MPLD
Investigation of the area reduction by pass transistor logic in reconfigurable device MPLD
2013
Yoshida Yuki
Michida Takumi
Tanigawa Kazuya
Hironaka Tetsuo
Shimomai Kenichi
Ishiguro Takashi
Keywords:
% area reduction
Field-programmable gate array
Electrical engineering
Pass transistor logic
Electronic engineering
Computer science
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