A Multi-Domain Architectural Efficiency Metric

Developments in the field of circuit design and computer architecture have introduced a variety of architectures such as in-memory compute, near-memory compute, FPGA, CGRA, DSP, GPU and many more still in the research phase. There is an increasing need for a unifying architectural efficiency metric that is applicable during the architecture design phase as well as post-silicon benchmarking, which quantifies different architectures, and is independent of the underlying implementation technology. This paper introduces an architectural efficiency metric that satisfies the above mentioned criteria. The metric quantifies the number of instructions or the size of reconfiguration bits required to perform a computation over a range of program sizes in the architecture. The metric helps understand limitations and benefits of different architectures, and provides insight into theoretical throughput. Our efficiency metric also informs the user/compiler about hardware options in a multi-architecture system based on the size of computation required.