16.2: A Parallel Digital‐Data‐Driver Architecture for Low‐Power Poly‐Si TFT‐LCDs

A parallel digital-data-driver architecture has been developed to reduce power consumption in low-temperature poly-Si TFT-LCDs. It features low-power 3V-interface level shifters and 198 serial/parallel converters driven in parallel at a clock frequency of 62.5 kHz. Total power consumption in a 2.4-in., 41K(176 × 234)-pixel TFT-LCD with integrated 6b DACs is 12 mW at a 30-Hz frame frequency.