INTRODUCING AN 150NM TECHNIQUE TO DECREASE AVERAGE POWER CONSUMPTION

In the present paper, we advise the style of the entire subtract or using GDI technique that will consume lesser power, exhibit greater speed therefore delivering a much better power delay product plus a reduced transistor count. Gate Diffusion Input (GDI) method is dependent on the effective use of an easy cell that you can use for low power digital circuits. This paper proposes the style of a power efficient, high-speed and occasional power full subtract or using Gate Diffusion Input (GDI) technique. The whole design continues to be performed in 150nm technology as well as on comparison having a full subtract or using the conventional CMOS transistors, transmission gates and Complementary Pass-Transistor Logic (CPL), correspondingly it's been discovered that there's a great deal of decrease in Average Power consumption (Pavg), delay time in addition to Power Delay Product (PDP). This process enables decrease in power consumption, propagation delay and transistor count of digital circuit. The technique may be used to minimize the amount of transistors when compared with conventional Complementary Pass-transistor Logic (CPL) and Dual Pass transistor Logic (DPL) CMOS design. Pavg is as little as 13.96nW as the delay time is discovered to be 18.02pico second therefore giving a PDP as little as 2.51x10-19 Joule for 1 volt power. Additionally for this there's a substantial decrease in transistor count when compared with traditional full subtract or employing CMOS transistors, transmission gates and CPL, accordingly implying minimization of area. The simulation from the suggested design continues to be transported in Tanner SPICE and also the layout continues to be developed in Micro wind.