Algorithmic and Protocol Level Countermeasures to Protect Cryptographic Devices

The main challenge in the field of embedded cryptographic devices is to develop cryptographic implementations which are resistant against both side-channel and fault attacks, while retaining acceptable security levels within budget and physical constraints. Although many countermeasures have been proposed in literature, no conclusive nor satisfactory solution has been found yet. This thesis provides a step forward towards the design and evaluation of algorithmic and protocol-level countermeasures, which offer combined resistance against side-channel and fault attacks.