High-performance BIMOS using self-aligning polysilicon electrode

To increase the speed of Hi-BiCMOS, the process of forming an electrode which simultaneously reduces both parasitic capacitance and parasitic resistance in MOSFET's and bipolar transistors was investigated. Since the etching rate of highly doped polycrystalline silicon is higher than undoped polycrystalline silicon, arsenic-doped polycrystalline silicon on the gate and emitter electrodes can be etched selectively. Self-aligned polycrystalline silicon electrode technology (SPEL) using this phenomena was proposed. When the As concentration in polycrystalline Si is higher than 4 × 1020 cm−3, the doped polycrystalline Si is etched 10 times faster than undoped polycrystalline Si if plasma etching based on chlorine radicals is carried out. Using this process, the drain capacitance of the MOSFET was reduced one-half to one-third that of conventional devices. In bipolar transistors, collector resistance was reduced by a factor of 2 and the external base resistance was reduced by a factor of 3. As a result of simulating the performance of the device formed by the SPEL process, the gate delay time in a dual input NAND BiCMOS was 0.19 ns under no-load condition while the gate delay time of the conventional device was 0.26 ns; that is, the speed of the SPEL device is 25 percent faster than that of the conventional device.