8.6fJ/step VCO-Based CT 2 nd -Order $\Delta\Sigma$ ADC

A purely VCO-based continuous-time (CT), single-loop second-order $\Delta\Sigma$ ADC is proposed in this work. Two ring oscillators are used as integrators to perform second-order quantization noise shaping. The proposed CT ADC does not require additional circuit for excess loop delay compensation. A current-reuse DAC architecture is proposed to simultaneously reduce ADC noise and power consumption. A 65nm prototype consumes $105\mu \mathbf{W}$ from 1V supply at sampling frequency of 32.6MHz, and achieves a walden FoM of 8.6fJ/step over 2.3MHz bandwidth, which is the best among current CT $\Delta\Sigma$ ADCs.