A low-power 12-bit 2nd-order Σ-Δ analog-to-digital converter for CMOS image sensors

A low-power and 12-bit resolution 2nd-order Σ-Δ ADC for CMOS image sensors is proposed. The proposed Σ-Δ ADC adopts the built-in correlated double sampling (CDS) technique and single-ended signaling to reduce the power consumption and chip area. The proposed Σ-Δ modulator of the ADC has the oversampling ratio (OSR) of 130 to achieve 12-bit resolution and the sampling rate of 1 0 M Hz to complete analog-to-digital conversion within 13 µs. The proposed ADC has been implemented using 0.35 µm 1P4M standard CMOS process. The simulation results using HSPICE show 75.8 dB SNDR and 210 µW power consumption under 2.8 V supply voltage.