Chip-type eelectric double layer capacitor and structure thereof

Disclosed is a package structure of a chip-type electric double layer capacitor which includes a lower package, which houses an electric double layer element and has a package terminal formed thereon to be electrically connected to the electric double layer element, and an upper package which is disposed on a top part of the lower package and seals the electric double layer element from the outside, wherein the package terminals are formed to be protruded from an internal bottom surface and an external bottom surface of the lower package, and the external bottom surface of the lower package has at least two pairs of protrusions formed thereon.