Monolithic integration of pseudo-spin-MOSFETs using a custom CMOS chip fabricated through multi-project wafer service

We demonstrated monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depended on the surface roughness of the passivation film. Nevertheless, after the chip surface was atomically flattened by SiO 2 deposition and successive chemical-mechanical polish (CMP) process, the fabricated MTJs on the surface exhibited a sufficiently large TMR ratio (> 140 %) adaptable to the PS-MOSFET application. The implemented PS-MOSFETs showed clear modulation of the output current controlled by the magnetization configuration of the MTJs, and a maximum magnetocurrent ratio of 90 % was achieved. These magnetocurrent behaviors were quantitatively consistent with those predicted by HSPICE simulations. The developed integration technique using a MPW CMOS chip would also be applied to monolithic integration of CMOS devices/circuits and other various functional devices/materials, which would open the door for exploring CMOS-based new functional hybrid circuits.