Multimode synchronous memory device and method of operation, and test methods thereof
2002
【Task】 A synchronous semiconductor memory device is operable in a normal mode and alternate mode. This semiconductor device has a plurality of input terminals for receiving the command bus, and a plurality of asynchronous input signals for receiving a plurality of input signals to be captured synchronously. The device further comprises a clock input for receiving an external clock signal, the device is to operate in normal mode using the external clock signal having a frequency not less than a predetermined minimum frequency, the manufacturer It has been designated by. The internal delay lock loop (DLL) clock circuit is coupled to a clock input terminal, the DLL clock circuit is in the normal operating mode, in response to the external clock signal, and generating at least one internal clock signal, wherein control circuitry in the device, in response to a predetermined sequence of asynchronous signals supplied to the asynchronous input terminals of the device, the device, in the alternative mode of operation to disable the internal clock signal, a result, this device it can operate in an alternative mode of using an external clock signal having a frequency lower than a predetermined minimum frequency. Wherein the alternative mode of operation, to facilitate testing of the device at a rate of less than the minimum frequency specified for the normal mode.
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