AW-SOM, an Algorithm for High-speed Learning in Hardware Self-Organizing Maps

Self-Organizing Maps (SOM) represent one of the most used clustering algorithms. A strong limitation in hardware SOM implementations is the decrease in processing speed when the number of neurons and features increase. For this reason, the literature provides different hardware solutions, often based on Field Programmable Gate Arrays (FPGAs). Unfortunately, even in these cases, the computing speed decreases as the number of neurons in the SOM increases. In this brief, authors present the All Winner-SOM (AW-SOM), a modified version of SOM algorithm. The proposed algorithm is suitable for hardware implementations and its main characteristic is a processing speed almost independent of the number of neurons reaching a 145 MHz clock within a range of 16 to 256 neurons. This feature allows to considerably increase the system performance in terms of computation rate.