A highly manufacturable high density embedded SRAM technology for 90 nm CMOS

A highly manufacturable high density embedded SRAM technology with a 0.8 /spl mu/m/sup 2/ cell for the 90 nm technology node has been developed. Based on a cell layout study by lithography simulation, both cell layout and key processes were carefully optimized and scaled down from those of 100 nm technology. The fabricated SRAM using 0.25 /spl mu/m well isolation and 0.1 /spl mu/m contacts showed good functionality down to VDD=0.6 V. An electrical fuse utilizing MOSFETs was also developed for redundancy to avoid Cu/low-k BEOL damage from laser blow.