Fast 2D convolution using reconfigurable computing

Convolution and its related counterpart correlation are two commonly used operations in image processing. However these operations are computationally expensive, and perform sluggishly when implemented on microprocessors. Part of the poor performance is due to the serial nature of microprocessors, while the operations of convolution and correlation are inherently parallel. One approach to implementing these operations in parallel is to build them in hardware using application specific integrated circuits (ASICs). Another approach is to use Field Programmable Gate Arrays (FPGAs) and reconfigurable computing. Reconfigurable computing offers a trade-off between the flexibility of software running on a microprocessor and the speed of custom designed hardware. This paper describes a parallel pipelined architecture for 2D convolution written in Handel-C for a reconfigurable computing platform. The resulting system offered a 400 times increase in speed over software written in C.