Effect of Sub-10nm Fin-widths on the Analog Performance of FinFETs

This work experimentally investigates the effect of fm-width $(W_{fin})$ scaling in sub-10nm regime on the analog performance of nFinFETs. It is shown that the device trans-conductance $(g_{m})$ degrades and output conductance $(g_{ds})$ improves with reduction in $W_{fin}.$ Various sources affecting the variability of $g_{m}$ and gds in sub-10nm $W_{fin}$ regime are also explored. Through different analog performance metrics, it is shown that the analog performance of thinner fin FinFETs can be further increased by properly optimizing the S/D resistance and gate dielectric.