PCM 메인 메모리 Lifetime 향상을 위한 캐쉬 교체 정책

Phase Change Memory (PCM) is one of the most promising technologies for non-volatile random access memory architectures. However, using PCM as a main memory technology is only possible if the write endurance problem is first solved effectively. With a PCM device, there is a limit on the number of times each bit cell can be written typically on the order of about 10 7 writes per bit cell. In this paper, we present a new cache line replacement policy for reducing the number of writes and thereby extending expected PCM lifetimes. Simulation results show that the proposed policy results in up to 63 % improvement in PCM lifetime over previously proposed methods.